HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

AW: humax digi+ iv

S4iyan3lit3 schrieb:

Hy Mate. How can u JTAG it ? desolder BGA processor ? or find jtag pins on panel :S iam stuck now with Digi + II :S i dontknow how continue ? desolder or simple find jtag pinouts ? or wtf ? first i need to connect up with preocessor aftert that use ejtag or jkeys for dump flash after this searching bk&rsa on dump with hex editor :S but mine receiver is only for test now. +extra lol where u got epoxy resin from DPS -.-' pfff

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jtag pins on panel read the eraly post entry from the begining and you will se that are images with the procesor

AW: humax digi+ iv

slyver schrieb:

my humax is different inside but the procesor and the flash are the same
and thanks allot for this post, next week i will jtag -it :good:
i will post the results

:good:

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have you successfully used/read via jtag the bk and rsa of this decoder?

AW: humax digi+ iv

jag_prz schrieb:

have you successfully used/read via jtag the bk and rsa of this decoder?

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i don't unerstand the c5 (tdi) what'is the line connection

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

sorry guys but c 5 line doesnt seems to spot enywhere ,i m stuck:smoke:



please help us to jtag this stb:emoticon-0150-hands

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

ciao a tutti,

slyver, anche io ho questo receiver(stesso processore, stessa flash) potresti dirmi come fai a identificare i vari segnali? I pin del processore sono nascosti... Se lo sapevo ti potevo aiutare in qualche modo.

Ma il programmatore di cui si parla nella prima pagina a cosa serve? Con google translator non sono riusito a capire.
Con gli altri receiver si dovevano disaldare i pin usati per il jtag, in questo caso si devono interrompere le piste?

Qualcuno è riuscito a trovare il tesoro che c'è dentro questo decoder??

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

dariu schrieb:

ciao a tutti,

slyver, anche io ho questo receiver(stesso processore, stessa flash) potresti dirmi come fai a identificare i vari segnali? I pin del processore sono nascosti... Se lo sapevo ti potevo aiutare in qualche modo.

Ma il programmatore di cui si parla nella prima pagina a cosa serve? Con google translator non sono riusito a capire.
Con gli altri receiver si dovevano disaldare i pin usati per il jtag, in questo caso si devono interrompere le piste?

Qualcuno è riuscito a trovare il tesoro che c'è dentro questo decoder??

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non e che sono cosi essperto pero se guardi bene le foto del primo post vedrai che gli 2 processori sono uguali e solo che uno e conexant e uno nxu, gli collegamenti sono ugulai.l`unico che manca e c5 non si trova.e non sono riuscito anora a provare interompere gli circuiti perche non ho fatto tutti gli collegamenti,
poi sono un NEWBIE non so tante cose percio lascio gli experti a mettersi in monstra pero mancano:dfingers::dfingers::dfingers::dfingers::dfingers:

First of all I personaly DJTomcro for the great work.

I didn't find a datasheet for cx24155-45mz but when I'am looking at and at Link veralten (gelöscht) it seems that the marked pins is wrong.

I don't know which is the corner from where it starts counting. I think that is the left-up corner on the top view. For me the top is the side where it is written the processor name and bottom is the pins side. There it's my problem.
For example intel p4 top/bottom is like I've just described it.
Looking at the second picture, DJTomcro has considered that the bottom is the written side.

I don't understand if Willem Programmer is necessary or jtag interface is enough?

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

Cann you give higher pickture

Re: AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

dino77 schrieb:

Cann you give higher pickture

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sorry, they are the same pictures that you can see in first page of this topic







And if I'm right, one of the jtag pins(B5 -TDO) isn't linked(blind).
Now i'm looking and I am thinking that the DJTomcro saw this pins on the left side but look below on the same side (eg. H25 H26) and you see that some pins aren't on the same side on the picture .

I'm hoping that I am wrong because this is a big problem.

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

Keep the post alive :emoticon-0137-clapp

AW: Re: AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

dariu schrieb:

sorry, they are the same pictures that you can see in first page of this topic

Du musst dich Anmelden oder Registrieren um diesen link zusehen!

Du musst dich Anmelden oder Registrieren um diesen link zusehen!

And if I'm right, one of the jtag pins(B5 -TDO) isn't linked(blind).
Now i'm looking

Du musst dich Anmelden oder Registrieren um diesen link zusehen!

and I am thinking that the DJTomcro saw this pins on the left side but look below on the same side (eg. H25 H26) and you see that some pins aren't on the same side on the picture

Du musst dich Anmelden oder Registrieren um diesen link zusehen!

.

I'm hoping that I am wrong because this is a big problem.

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Same to me. If this is the Bottom view pins have to be mirrored

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

If I do jtag with pins do I must desolder the CPU ?

Can some explain much better tnx for the post but it's not good explained

if u read better you see that nobody told that has jtaged it. this is a project

hi guys, i've found the datasheet for this processor,
Link veralten (gelöscht)

Du musst dich Anmelden oder Registrieren um diesen link zusehen!

good luck but it seems impossibile to jtag it: b5(TDO), c5(TDI) are blind and a4(TCK), a5(TMS), c6(TRST) probably are linked to the ground. So is Jtag protected.
If someone have any idea is welcome. I'm asking how did polish man do his "work".
Disolding flash is more difficult because is smaller...any suggestins?

AW: HowTo BK & RSA von Humax Digi+ IV (III & II) Beta

C6 TRST# Test Reset / Mode Enable. Initializes the JTAG
tap controllers. This pin should be driven by
the external power on reset controller circuit
when the chip is connected to an external
JTAG interface device.
Designs not using the JTAG interface may tie
this pin directly to ground.
pd_pio_r I
A5 TMS JTAG test mode select for the JTAG tap
controllers. Transitions on this pin drive the
JTAG state machine through its sequences.
This pin should be pulled high with a 10kohm
resistor when connected to an external JTAG
interface device.
Designs not using the JTAG interface may
float this pin and rely on the internal pullup or
tie the pin directly to the VDDIO supply rail.
pd_pio_r I
B5 TDO JTAG test data output.
Designs not using the JTAG interface must
leave this pin floating.
Do not attach external pullup or pulldown
resistors to this pin.
pd_pio_m O
C5 TDI JTAG test data input. Loads instructions into
the TAP controller or loads test vector data
for boundary-scan operation. This pin should
be pulled high with a 10kohm resistor when
connected to an external JTAG interface
device.
Designs not using the JTAG interface may
float this pin and rely on the internal pullup or
tie the pin directly to the VDDIO supply rail.
pd_pio_r I
A4 TCK JTAG test clock. Used to synchronize all
JTAG test structures. Pin should be pulled
low with a 10kohm resistor when connected
to an external JTAG interface device.
Designs not using the JTAG interface may tie
this pin directly to ground.
pd_pio I
AD9 CHIP_TEST# CHIP_TEST# pin used for automated testing
purposes only. Customer designs should
leave this pin floating.
pd_pio_r I